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1 ? ISL6554 microprocessor core voltage regulator using multi-phase buck pwm control without programmable droop the ISL6554 is the first controll er in the intersil multi-phase family without the programmable droop feature. the ISL6554 in combination with the hip6601a, hip6602a or hip6603a companion gate drivers and intersil mosfets form a complete solution for high-current, high slew-rate applications. the ISL6554 regulates output voltage, balances load currents and provid es protective functions for two to four synchronous-rectified buck-converter channels. a novel approach to current sensing is used to reduce overall solution cost. the voltage developed across the lower mosfet?s parasitic on-resistance during conduction is sampled and fed back to the controller. this lossless current-sensing approach allows the controller to maintain phase-current balance between the power channels and overcurrent protection. a 5-bit dac allows digital programming of the output voltage in 25mv steps over a range from 0.95v to 1.70v with a system accuracy of 1%. internal pull ups on each dac input make external pull-up resistors unnecessary when interfacing with open-drain output signals. the pgood signal is held low during soft-start until the output voltage increases to wit hin 4% of the programmed. when the core voltage falls 9% below the programmed vid level, an undervoltage condition is detected and results in pgood transitioning low. in the event of an overvoltage condition, the converter shuts down and turns on the lower mosfets to clamp and protect the microprocessor. overcurrent protection reduces the regulator rms output current to 41% of the programmed overcurrent trip value. these features provide monitoring and protection for the micr oprocessor and power system. pinout ISL6554 (soic) top view features ? multi-phase power conversion ? precision channel current balance - lossless current sampling - uses r ds(on) ? precision core voltage regulation - 1% system accuracy over temperature - no programmable droop ? microprocessor voltag e identification input - 5-bit vid decoder - 0.95v to 1.70v in 25mv steps ? fast transient response ? overcurrent protection ? selection of 2, 3, or 4 phase operation ? high ripple frequency (80khz to 2mhz) ? pb-free available applications ? power supply controller fo r intel? itanium? processor family ? voltage regulator modules ? servers and workstations 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis pwm2 pgood pwm3 isen4 isen1 vcc gnd isen3 fb pwm4 vsen comp pwm1 isen2 ordering information part number temp. (c) package pkg. dwg. # ISL6554cb 0 to 70 20 ld soic m20.3 ISL6554cb-t 20 ld soic tape and reel ISL6554cbz (note) 0 to 70 20 ld soic (pb-free) m20.3 ISL6554cbz-t (note) 20 ld soic tape and reel (pb-free) ISL6554cbza (note) 0 to 70 20 ld soic (pb-free) m20.3 ISL6554cbza-t (note) 20 ld soic tape and reel (pb-free) note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. fn9003.2 data sheet july 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001, 2004. all rights reserved. intel? is a registered trademark of intel corporation. itanium? is a trademark of intel corporation. all other trademarks mentioned are the property of their respective owners.
2 block diagram d/a current correction ov latch power-on reset (por) soft- start and fault logic channel detector uv ovp e/a pwm oc pwm1 pwm2 pwm3 pwm4 gnd pgood vcc fb i_trip fs/en s state i_tot + - + - + - + + + + phase clock and number three vid4 vid3 vid2 vid1 comp vsen generator sawtooth x1.15 x 0.9 isen1 isen2 isen3 isen4 vid0 + - + - + - + - pwm + - pwm + - + - + - pwm + - ISL6554
3 simplified power system diagram functional pin description vid4 (pin 1), vid3 (pin 2), vid2 (pin 3), vid1 (pin 4) and vid0 (pin 5) voltage identification inputs from microprocessor. these pins respond to ttl and 3.3v logic signals. the ISL6554 decodes vid bits to establish the output voltage. see table 1. comp (pin 6) output of the internal error amplifier. connect this pin to the external feedback and compensation network. fb (pin 7) inverting input of the in ternal error amplifier. fs/dis (pin 8) channel frequency, f sw , select and disable. a resistor from this pin to ground sets th e switching frequency of the converter. pulling this pin to ground disables the converter and three states the pwm outputs. see figure 10. gnd (pin 9) bias and reference ground. all signals are referenced to this pin. vsen (pin 10) power good monitor input. connect to the microprocessor- core voltage. pwm1 (pin 15), pwm2 (pin 14), pwm3 (pin 11) and pwm4 (pin 18) pwm outputs for each driven channel in use. connect these pins to the pwm input of an hip6601/2/3 driver. for systems which use 3 channels, connect pwm4 high. two channel systems connect pwm3 and pwm4 high. isen1 (pin 16), isen2 (pin 13), isen3 (pin 12) and isen4 (pin 17) current sense inputs from the individual converter channel?s phase nodes. unused sense lines must be left open. pgood (pin 19) power good. this pin provides a logic-high signal when the microprocessor core voltage is within specified limits and soft-start has timed out. vcc (pin 20) bias supply. connect this pin to a 5v supply. synchronous ISL6554 microprocessor vsen vid rectified buck channel synchronous rectified buck channel synchronous rectified buck channel synchronous rectified buck channel pwm 1 pwm 2 pwm 3 pwm 4 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis pwm2 pgood pwm3 isen4 isen1 vcc gnd isen3 fb pwm4 vsen comp pwm1 isen2 ISL6554
4 typical application - 2 phase con verter using hip6601 gate drivers main control ISL6554 vid4 vid1 pgood fb +5v comp pwm3 pwm2 pwm1 isen3 isen2 isen1 vsen driver hip6601 pwm vcc boot ugate phase lgate v in = +5v pvcc pwm vcc boot ugate phase lgate v in = +5v driver hip6601 pvcc fs/dis pwm4 isen4 nc gnd gnd gnd vcc +v core nc +12v +12v vid3 vid0 vid2 ISL6554
5 typical application - 4 phase con verter using hip6602 gate drivers vid4 vid3 vid2 vid1 fb +5v comp pwm1 pwm2 isen2 pwm3 pwm4 isen4 vsen fs/dis isen1 isen3 gnd v in +12v boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm1 pvcc +5v vcc v in = +12v +12v dual driver hip6602 v in +12v boot4 ugate4 phase4 lgate4 boot3 ugate3 phase3 lgate3 pwm3 pvcc +5v vcc v in +12v +12v dual driver hip6602 pgood gnd gnd vcc +v core l 01 l 02 l 03 l 04 pwm2 pwm4 main control ISL6554 vid0 ISL6554
6 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v input, output, or i/o voltage . . . . . . . . . . gnd -0.3v to vcc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv recommended operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 125c thermal information thermal resistance (typical, note 1) ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications operating conditions: vcc = 5v, t a = 0c to 70c, unless otherwise specified parameter test conditions min typ max units input supply power input supply current r t = 100k ? -1015ma power-on reset (por) vcc rising threshold 4.25 4.38 4.5 v vcc falling threshold 3.75 3.88 4.00 v reference and dac reference voltage accuracy -1 - 1 % dac pin input low voltage threshold --0.8v dac pin input high voltage threshold 2.0 - - v vid pull-up vidx = 0v or vidx = 3v 10 20 40 a oscillator frequency, f sw r t = 100k ? , 1% 224 280 336 khz adjustment range see figure 10 0.05 - 1.5 mhz disable voltage maximum voltage at fs /dis to disable controller. i fs/dis = 1ma. - 1.2 1.0 v error amplifier dc gain r l = 10k to gnd - 72 - db gain-bandwidth product c l = 100pf, r l = 10k to gnd - 18 - mhz slew rate c l = 100pf, r l = 10k to gnd - 5.3 - v/ s maximum output voltage r l = 10k to gnd 3.6 4.1 - v minimum output voltage r l = 10k to gnd - 0.16 0.5 v isen full scale input current -50- a overcurrent trip level - 82.5 - a power good upper threshold vsen rising 0.95 0.97 0.99 v dac lower threshold vsen falling 0.89 0.91 0.93 v dac pgood low output voltage i pgood = 4ma - 0.18 0.4 v protection overvoltage threshold vsen rising 1.12 1.15 1.2 v dac percent overvoltage hysteresis vsen falling after overvoltage - 2 - % ISL6554
7 operation figure 1 shows a simplified diagram of the voltage regulation and current control loops. both voltage and current feedback are used to precisely regulate voltage and tightly control output currents, i l1 and i l2 , of the two power channels. the voltage loop comprises the error amplifier, comparators, gate drivers and output mosfets. the error amplifier is essentially connected as a voltage follower that has as an input, the programmable refe rence dac and an output that is the core voltage. voltage loop feedback from the core voltage is applied via resistor r in to the inverting input of the error amplifier. this signal can drive the error amplifier output either high or low, depending upon the core voltage. low core voltage makes the amplifier output move towards a higher output voltage level. amplifier output voltage is applied to the positive inputs of the comparators via the correction summing networks. out-of-phase sawtooth signals are applied to the two comparators inverting inputs. increasing error amplifier voltage results in increased co mparator output duty cycle. this increased duty cycle signal is passed through the pwm circuit with no phase reversal an d on to the hip6601, again with no phase reversal for gate drive to the upper mosfets, q1 and q3. increased duty cycle or on time for the mosfet transistors results in increased output voltage to compensate for the low output voltage sensed. current loop the current control loop works in a similar fashion to the voltage control loop, but with current control information applied individually to each channel?s comparator. the information used for this cont rol is the voltage that is developed across r ds(on) of each lower mosfet, q2 and q4, when they are conducting. a single resistor converts and scales the voltage across the mosfets to a current that is applied to the current sensing circuit within the ISL6554. output from these sensing circ uits is applied to the current averaging circuit. each pwm channel receives the difference current signal from the summing circuit that compares the average sensed current to the individual channel current. when a power channel?s current is greater than the average current, the signal applied via the summing correction circuit to the compar ator, reduces the output pulse width of the comparator to compensate for the detected ?above average? current in that channel. current sensing comparator pwm circuit + r isen1 + correction error amplifier fb reference isen1 r in v core q3 q4 l2 phase pwm1 i l2 dac ISL6554 c out r load v in hip6601 - q1 q2 l1 phase i l1 v in hip6601 current sensing comparator pwm circuit correction pwm2 - i average + + - programmable r isen2 isen2 - current averaging figure 1. simplified block diagram of the ISL6554 voltage and current contro l loops for a two power channel regulator + - + - + - ISL6554
8 applications and converter start-up each pwm power channel?s current is regulated. this enables the pwm channels to accurately share the load current for enhanced reliability . the hip6601, hip6602 or hip6603 mosfet driver interf aces with the ISL6554. for more information, see the hi p6601, hip6602 or hip6603 data sheets [1], [2]. the ISL6554 is capable of controlling up to 4 pwm power channels. connecting unused pwm outputs to vcc automatically sets the numbe r of channels. the phase relationship between the chann els is 360 degrees/number of active pwm channels. for example, for three channel operation, the pwm outputs are separated by 120 degrees. figure 2 shows the pwm output signals for a four channel system. power supply ripple frequency is determined by the channel frequency, f sw , multiplied by the number of active channels. for example, if the channel frequency is set to 250khz and there are three phases, the ripple frequency is 750khz. the ic monitors and precisely regulates the core voltage of a microprocessor. after initia l start-up, the controller also provides protection for the load and the power supply. the following section discu sses these features. initialization the ISL6554 usually operates from an atx power supply. many functions are initiated by the rising supply voltage to the vcc pin of the ISL6554. o scillator, sawtooth generator, soft-start and other functions are initialized during this interval. these circuits are controlled by por, power-on reset. during this interval, the pwm outputs are driven to a three state condition that ma kes these outputs essentially open. this state results in no gate drive to the output mosfets. once the vcc voltage reaches 4.375v ( + 125mv), a voltage level to insure proper internal function, the pwm outputs are enabled and the soft-start sequenc e is initiated. if for any reason, the vcc voltage drops below 3.875v ( + 125mv). the por circuit shuts the converter down and again three states the pwm outputs. soft-start after the por function is completed with vcc reaching 4.375v, the soft-start sequence is initiated. soft-start, by its slow rise in core voltage from zero, avoids an overcurrent condition by slowly char ging the discharged output capacitors. this voltage rise is initiated by an internal dac that slowly raises the referenc e voltage to the error amplifier input. the voltage rise is controlled by the oscillator frequency and the dac within the ISL6554, therefore; the output voltage is effectively regulated as it rises to the final programmed core voltage value. for the first 32 pwm switching cycles, the dac output remains inhibited and the pwm outputs remain three stated. from the 33rd cycle and for another, approx imately 150 cycles, the pwm output remain s low, clamping the lower output mosfets to ground (see figure 3). the time variability is due to the error amplifier, sawtooth generator and comparators moving into their active regions. after this short interval, the pwm outputs are enabled and increment the pwm pulse width from ze ro duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the core voltage. the co re voltage will reach its programmed value before th e 2048 cycles, but the pgood output will not be initiated until the 2048th pwm switching cycle. the soft-start time or delay time, dt = 2048/f sw . for an oscillator frequency, f sw , of 200khz, the first 32 cycles or 160 s, the pwm outputs are held in a three state level as explained above. after this period and a short interval described above, the pwm outputs are initiated and the voltage rises in 10.08ms, for a total delay time dt of 10.24ms. figure 3 shows the start-up sequence as initiated by a fast rising 5v supply, vcc , applied to the ISL6554. note the short rise to the three state level in pwm 1 output during first 32 pwm cycles. figure 4 shows the waveforms when the regulator is operating at 200khz. note that the soft-start duration is a function of the channel frequency as explained previously. also note the pulses on the comp terminal. these pulses are the current correction signal feeding into the comparator input (see the block diagram ). figure 5 shows the regulator operating from an atx supply. in this figure, note the slight rise in pgood as the 5v supply rises. the pgood output stag e is made up of nmos and pmos transistors. on the rising vcc, the pmos device becomes active slightly befor e the nmos transistor pulls ?down?, generating the slight rise in the pgood voltage. pwm 1 pwm 2 pwm 3 pwm 4 figure 2. four phase pwm output at 500khz ISL6554
9 note that figure 5 shows the 12v gate driver voltage available before the 5v supply to the ISL6554 has reached its threshold level. if conditions were reversed and the 5v supply was to rise first, the start-up sequence would be different. in this case the ISL6554 will sense an overcurrent condition due to charging the output capacitors. the supply will then restart and go through the normal soft-start cycle. fault protection the ISL6554 protects the microprocessor and the entire power system from damaging stress levels. within the ISL6554 both overvoltage and overcurrent circuits are incorporated to protect the load and regulator. overvoltage the vsen pin is connected to the microprocessor core voltage. a core overvoltage condition is detected when the vsen pin goes more than 15 % above the programmed vid level. the overvoltage condition is latched, disabling normal pwm operation, and causing pgood to go low. the latch can only be reset by lowering and returning vcc high to initiate a por and soft-start sequence. during a latched overvoltage, the pwm outputs will be driven either low or three state, depending upon the vsen input. pwm outputs are driven low when the vsen pin detects that the core voltage is 15% above the programmed vid level. this condition drives the pwm outputs low, resulting in the lower or synchronous rectifier mosfets to conduct and shunt the core voltage to ground to protect the load. if after this event, the core voltage falls below the over- voltage limit (plus some hysteresis), the pwm outputs will three state. the hip6601 family drivers pass the three-state information along, and shuts off both upper and lower mosfets. this prevents ?dumping? of the output capacitors back through the lower mosfets, avoiding a possibly destructive ringing of the capacitors and output inductors. if the conditions that caused the overvoltage still persist, the pwm outputs will be cycled between three state and v core clamped to ground, as a hysteretic shunt regulator. undervoltage the vsen pin also detects when the core voltage falls more than 9% below the vid programmed level. this causes pgood to go low, but has no other effect on operation and is not latched. there is also hyst eresis in this detection point. overcurrent in the event of an overcurrent condition, the overcurrent protection circuit reduces the rms current delivered to 41% of the current limit. when an overcurrent condition is detected, the controller forces all pwm outputs into a three state mode. this condition results in the gate driver removing drive to the output stages. the ISL6554 goes into a wait delay timing cycle that is equal to the soft-start ramp pwm 1 pgood v core 5v output vcc v in = 12v delay time figure 3. start-up of 4 phase system operating at 500khz pgood v core 5v v comp vcc v in = 12v delay time figure 4. start-up of 4 phase system operating at 200khz 12v atx supply pgood 5 v atx v core supply atx supply activated by atx ?ps-on pin? v in = 5v, core load current = 31a figure 5. supply powered by atx supply frequency 200khz ISL6554
10 time. pgood also goes ?low? during this time due to vsen going below its threshold voltage. to lower the average output dissipation, the soft-start initial wait time is increased from 32 to 2048 cycles, then the soft-start ramp is initiated. at a pwm frequency of 200khz, for instance, an overcurrent detection would cause a dead ti me of 10.24ms, then a ramp of 10.08ms. at the end of the delay, pwm outputs are restarted and the soft-start ramp is init iated. if a short is present at that time, the cycle is repeated. this is the hiccup mode. figure 6 shows the supply shor ted under operation and the hiccup operating mode described above. note that due to the high short circuit current, overcurrent is detected before completion of the start-up sequence so the delay is not quite as long as the normal soft-start cycle. core voltage programming the voltage identification pins (vid0, vid1,vid2,vid3 and vid4) set the core output volta ge. each vid pin is pulled to vcc by an internal 20 a current source and accepts open- collector/open-drain/open-swit ch-to-ground or standard low- voltage ttl or cmos signals. table 1 shows the nominal dac voltage as a function of the vid codes. the power supply system is 1% accurate over the operating temperature and voltage range. current sensing and balancing overview the ISL6554 samples the on-state voltage drop across each synchronous rectifier mosfet, q2, as an indication of the inductor current in that phase (s ee figure 7). neglecting ac effects (to be discussed later), the voltage drop across q2 is simply r ds(on) (q2) x inductor current (i l ). note that i l , the inductor current, is either 1/2, 1/3, or 1/4 of the total current (i lt ), depending on how many phases are in use. the voltage at q2?s drain, the phase node, is applied to the r isen resistor to develop the i isen current to the ISL6554 isen pin. this pin is held at virtual ground, so the current through r isen is i l x r ds(on) (q2) / r isen . the i isen current provides information to perform the following functions: 1. detection of an overcurrent condition 2. balance the i l currents in multiple channels overcurrent, selecting risen the current detected through the r isen resistor is averaged with the current(s) detected in the other 1, 2, or 3 channels. the averaged curr ent is compared with a trimmed, internally generated current, and used to detect an overcurrent condition. table 1. voltage identification codes voltage identification code at processor pins vcc core (v dc ) vid4 vid3 vid2 vid1 vid0 1 1111output off 1 11100.95 1 11010.975 1 11001.000 1 10111.025 1 10101.050 1 10011.075 1 10001.100 1 01111.125 pgood short 50a/div. curren t atx supply activated by atx ?ps-on pin? supply frequency = 200khz, v in = 12v hiccup mode. supply powered by atx supply core load current = 31a, 5v load = 5a short applied here figure 6. short applied to supply after power-up 1 01101.150 1 01011.175 1 01001.200 1 00111.225 1 00101.250 1 00011.275 1 00001.300 0 11111.325 0 11101.350 0 11011.375 0 11001.400 0 10111.425 0 10101.450 0 10011.475 0 10001.500 0 01111.525 0 01101.550 0 01011.575 0 01001.600 0 00111.625 0 00101.650 0 00011.675 0 00001.700 table 1. voltage identification codes (continued) voltage identification code at processor pins vcc core (v dc ) vid4 vid3 vid2 vid1 vid0 ISL6554
11 the nominal current through the r isen resistor should be 50 a at full output load current, and the nominal trip point for overcurrent detection is 165% of that value, or 82.5 a. therefore, r isen = i l x r ds(on) (q2) / 50 a. for a full load of 25a per phase, and an r ds(on) (q2) of 4m ? , r isen = 2k ? . the overcurrent trip point woul d be 165% of 25a, or ~ 41a per phase. the r isen value can be adjusted to change the overcurrent trip point, but it is suggested to stay within 25% of nominal. current balancing the detected currents are also used to balance the phase currents. each phase?s current is compared to the average of all phase currents, and the difference is used to create an offset in that phase?s pwm comparator. the offset is in a direction to reduce the imbalance. the balancing circuit can not make up for a difference in r ds(on) between synchronous rectifiers. if a fet has a higher r ds(on) , the current through that phase will be reduced. figures 8 and 9 show the inductor current of a two phase system without and with current balancing. inductor current the inductor current in each phase of a multi-phase buck converter has two components. there is a current equal to the load current divided by the number of phases (i lt / n), and a sawtooth current, (i pk-pk ) resulting from switching. the sawtooth component is de pendent on the size of the inductors, the switching frequency of each phase, and the values of the input and outpu t voltage. ignoring secondary effects, such as series resistance, the peak to peak value of the sawtooth current can be described by: i pk-pk = (v in x v core - v core 2 ) / (l x f sw x v in ) where: v core = dc value of the output or v id voltage v in = dc value of the input or supply voltage l= value of the inductor f sw = switching frequency example: for v core = 1.6v, v in = 12v, l= 1.3 h, f sw = 250khz, then i pk-pk = 4.3a the inductor, or load current, flows alternately from v in through q1 and from ground through q2. the ISL6554 samples the on-state voltage drop across each q2 transistor to indicate the inductor current in that phase. the voltage drop is sampled 1/3 of a switching period, i/f sw , after q1 is turned off and q2 is turned on. because of the sawtooth current component, the sampled cu rrent is different from the average current per phase. neglecting secondary effects, the sampled current (i sample ) can be related to the load current (i lt ) by: i sample = i lt / n + (v in v core -3v core 2 ) / (6l x f sw x v in ) where: i lt = total load current n = the number of channels example: using the previously given conditions, and for i lt = 100a, n = 4 then i sample = 25.49a figure 7. simplified functional block diag ram showing current and voltage sampling current sensing comparator pwm circuit averaging current from other channels sawtooth generator + difference r isen + correction error amplifier fb comp reference to other channels isen r in r fb c c v core q1 q2 comparator reference to over current trip l 01 phase inductor current(s) from other channels pwm i l dac ISL6554 c out r load v in only one output hip6601 - - stage shown sensing + - + - + - ISL6554
12 as discussed previously, the voltage drop across each q2 transistor at the point in time when current is sampled is r dson (q2) x i sample . the voltage at q2?s drain, the phase node, is applied through the r isen resistor to the ISL6554 isen pin. this pin is held at virtual ground, so the current into isen is: i sense = i sample x r ds(on) (q2) / r isen . r isen = i sample x r ds(on) (q2) / 50 a example: from the previous conditions, where i lt = 100a, i sample = 25.49a, r ds(on) (q2) = 4m ? then: r isen = 2.04k and i current trip = 165% short circuit i lt = 165a. channel frequency oscillator the channel oscillator frequency is set by placing a resistor, r t , to ground from the fs/dis pin. figure 10 is a curve showing the relationship between frequency, f sw , and resistor r t . to avoid pickup by the fs/dis pin, it is important to place this resistor next to the pin. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an exam ple, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. contact intersil for evaluation board drawings of the component placement and printed circuit board. there are two sets of critical components in a dc-dc converter using a ISL6554 controller and a hip6601 gate driver. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed first. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. locate the output inductors and output capacitors between the mosfets and the load. locate the gate driver close to the mosfets. the critical small components include the bypass capacitors for vcc and pvcc on the gate dr iver ics. locate the bypass capacitor, c bp , for the ISL6554 controller close to the device. it is especially important to locate the resistors associated with the input to the amplifiers close to their respective pins, since they represent the input to f eedback amplifiers. resistor r t , that sets the oscillator frequency should also be located next to the associated pin. it is espec ially important to place the r sen resistors at the respective terminals of the ISL6554. a multi-layer printed circuit board is recommended. figure 11 shows the connections of the critical components for one output channel of the converter. note that capacitors c in and c out could each represent numer ous physical capacitors. dedicate one solid layer, usually the middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to output i nductor short. the power plane should support the input power and output power nodes. use 0 5 10 15 20 25 amperes figure 8. two channel multi-phase system with current balancing disabled 0 5 10 15 20 25 amperes figure 9. two channel multi-phase system with current balancing enabled ISL6554
13 copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring trac es from the driver ic to the mosfet gate and source should be sized to carry at least one ampere of current. component selection guidelines output capacitor selection the output capacitor is selected to meet both the dynamic load requirements and the voltage ripple requirements. the load transient for the micropro cessor core is characterized by high slew rate (di/dt) current demands. in general, multiple high quality capacitors of different size and dielectric are paralleled to meet the design constraints. modern microprocesso rs produce severe transient load rates. high frequency capacitors supply the initially transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor valu es are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr determines the output ripple voltage and the initial voltage drop following a high slew-rate transient?s edge. in mo st cases, multiple capacitors of small case size perform better than a single large case capacitor. bulk capacitor choices inclu de aluminum electrolytic, os- con, tantalum and even ceramic dielectrics. an aluminum electrolytic capacitor?s esr valu e is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a spec ified parameter. consult the capacitor manufacturer and measure the capacitor?s impedance with frequency to select a suitable component. output inductor selection one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. small inductors in a multi-phase converter reduces the response time without signif icant increases in total ripple current. the output inductor of each power channel controls the ripple current. the control ic is stable for channel ripple current (peak-to-peak) up to twice the average current. a single channel?s ripple current is approximately: the current from multiple channel s tend to cancel each other and reduce the total ripple current. figure 12 gives the total ripple current as a function of duty cycle, normalized to the parameter at zero du ty cycle. to determine the total ripple current from th e number of channels and the duty cycle, multiply the y-axis value by . small values of output inductance can cause excessive power dissipation. the ISL6554 is designed for stable operation for ripple currents up to twice the load current. however, for this condition, the rms current is 115% above the value shown in the following mosfet selection and considerations section. with all else fixed, decreasing the inductance could increase the power dissipated in the mosfets by 30%. 50 100 10 20 200 500 1,000 5,000 10,000 2,000 1 2 5 10 20 50 100 200 500 1,000 r t (k ? ) channel oscillator frequency, f sw (khz) figure 10. resistance r t vs frequency ? i v in v out ? f sw l ------------------------------- - v out v in --------------- - = vo () lxf sw () ? vo () lxf sw () ? 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) ripple current (a peak-peak ) v o / (l x f sw ) single channel 2 channel 3 channel 4 channel figure 11. ripple current vs duty cycle ISL6554
14 input capacitor selection the important parameters for t he bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current required for a multi-phase converter can be approximated with the aid of figure 13. first determine the operating du ty ratio as the ratio of the output voltage divided by the input voltage. find the current multiplier from the curve with the appropriate power channels. multiply the current multiplier by the full load output current. the resulting value is the rms current rating required by the input capacitor. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors should be placed very close to the drain of t he upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for bulk capacitance, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge- current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selection and considerations in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty factor (see the following equations). the conduction losses are the main component of power dissipation for the lower mosfets, q2 and q4 of figure 1. only the upper mosfets, q1 and q3 have significant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfets body diode. the gate-charge losses are dissipated by the driver ic and don?t heat the mosfets. however, large gate-charge in creases the switching time, v core +12v via connection to ground plane island on power plane layer island on circuit plane layer l o1 c out c in +5v in key phase vcc use individual metal runs comp ISL6554 pwm r t r in r fb c bp fb vsen isen r sen hip6601 c boot c bp c t vcc fs/dis pvcc locate next to ic pin locate next to fb pin locate next to ic pin(s) isolate output stages for each channel to help locate near transistor figure 12. printed circuit board power planes and islands 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) current multiplier single channel 3 channel 4 channel 2 channel figure 13. current multiplier vs duty cycle ISL6554
15 t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at hi gh ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. a diode, anode to ground, may be placed across q2 and q4 of figure 1. these diodes func tion as a clamp that catches the negative inductor swing during the dead time between the turn off of the lower mosfets and the turn on of the upper mosfets. the diodes mu st be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is usually acceptab le to omit the diodes and let the body diodes of the lower mosfets clamp the negative inductor swing, but efficiency could drop one or two percent as a result. the diode?s rated reverse breakdown voltage must be greater than the maximum input voltage. references intersil documents are available on the web at www.intersil.com/ [1] hip6601/hip6603 data sheet , intersil corporation, file no. 4819 [2] hip6602 data sheet , intersil corporation, file no. 4838 p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f sw 2 --------------------------------------------------------- - + = p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = ISL6554
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6554 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.014 0.019 0.35 0.49 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 1 1/02

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